I have been very busy in the Folknology labs working through tens of different designs and boards as part of the Amino project. I am now at a point where I have a design for the first candidate Amino board – Amino Alpha. Below is an image of the boards layout, with highlighted I/O connectors, let me briefly show you around.
For communications we have full speed USB (480Mb/sec) and 10/100Bt Ethernet, the connectors for these can be seen to the north of the board. There is also a serial comms connector “C” to the left of the Ethernet RJ45, this houses dedicated UART and I2C pins. Also notice there is an optional MicroSD card slot underneath the mini USB connector facing northwards.
Interface “A” on the westside of the board provides a minimum 4 channel multiplexed analogue interface (we may add more channels here), based around a 10bit successive approximation ADC which is buffered over SPI, offering minimum conversion time of approximately 2.5 microseconds.
Alpha provides 2 high bandwidth nibble ports “B” and “D” to the south of the board, with channels capable of shifting up to 50MB/sec. Each port contains 4 1 bit bidirectional I/O pins and a single 4 bit bidirectional (nibble) channel. Together they provide effectively 16 bits of bidirectional I/O. In addition we have 3 further I/O pins which are currently uncommitted (we are currently reserving their use for more complex peripherals and a more modular expansion scheme), these sit between ports B and D along with some power and control pins.
To the west of the board lies interface J, providing a set of JTAG pins which can be used with Xtag or Xtag2 boards connected with only minor modifications/adaptors. This interface is used to debug the management and communication layer of the Amino stack and is not used for either regular participant space development or low level hardware layer development. Both of these development layers are debugged onboard without the need of an extra Jtag/Xtag adaptor. But obviously for ourselves and other alpha geeks this additional debug option is crucial. I will talk more about the layers in the Amino stack in a separate post later.
The main meat inside is obviously the brain and the nervous system made up of 2 XMOS XS1 L-64 chips. One of which (East) provides the nervous system, handles the low level I/O and Ethernet systems space, East is responsible for running low level layer 1 code which will conform to a modular service interface which unlike operating system drivers gets out of your way. The other (West) the brain, manages the entire Amino system including comms (TCP/IP,USB,Serial), memory and participant sketch/application space. The other chips handle lower level PHY, comms and ADC hardware.
I will be sharing the schematics over the next few days to provide more detail and feedback, in the meantime let me know your thoughts. I am still routing the boards so there may be some subtle changes before the first prototypes are made, but generally it should be very similar.
P.S. We are also considering a more robust industrial version which could add Canbus + CANopen, POE and grade 5 components for more harsh environments, if that’s of interest let me know.